ICS541

PLL Clock Divider

MDS 541 B

2

Revision 082500

Printed 11/14/00

Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

Pin Assignment

Number

Name

Type

Description

1

ICLK

CI

Clock input.

2

VDD

P

Connect to +3.3V or +5V.

3

GND

P

Connect to ground.

4

S0

I

Select 0 for output clock. Connect to GND or VDD, per decoding table above.

5

S1

I

Select 1 for output clock. Connect to GND or VDD, per decoding table above.

6

OE

I

Output Enable. Tri-states both output clocks when low.

7

CLK/2

O

Clock output per Table above. Low skew divide by two of pin 8 clock.

8

CLK

O

Clock output per Table above.

Pin Descriptions

Key: CI = clock input, I = input, O = output, P = power supply connection

Clock Decoding Table

0 = connect directly to ground.

1 = connect directly to VDD.

S1

S0

CLK

CLK/2

#5

#4

pin #8

pin #7

0

0

Power Down All

Power Down All

0

1

Input/4

Input/8

1

0

Input

Input/2

1

1

Input/2

Input/4

1

8

2

3

4

7

6

5

ICLK

GND

CLK

VDD

S1

8 pin SOIC

S0

CLK/2

OE

External Components

The ICS541 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must

be connected close to the ICS541 to minimize lead inductance. No external power supply filtering is

required for this device. A 33

Ω terminating resistor can be used next to each output pin. If a 3.3 V input

clock is applied to the ICLK pin, with the ICS541 at 5 V, the clock must be AC coupled.