ICS543

Clock Divider and 2X Multiplier

MDS 543 A

1

Revision 010599

Printed 12/4/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

I C R O

PRELIMINARY INFORMATION

• Packaged in 8 pin SOIC

• Low cost clock divider and 2X multiplier

• Low skew (500ps) outputs. One is ÷ 2 of other.

• Easy to use with other generators and buffers

• Input clock frequency up to 90 MHz at 5 V

• Output clock duty cycle of 45/55

• Power Down turns off chip

• Output Enable

• Full CMOS clock swings with 25 mA drive

capability at TTL levels

• Advanced, low power CMOS process

• Operating voltages of 3.0 to 5.5 V

The ICS543 is a cost effective way to produce a

high quality clock output divided from a clock

input. The chip accepts a clock input up to

90 MHz at 5.0 V, and by using proprietary Phase

Locked Loop (PLL) techniques, produces a divide

by 3, 5, 6, or 10, or a multiply by 2 of the input

clock. There are two outputs on the chip, one

being a low-skew divide by two of the other. So,

for instance, if an 81 MHz input clock is used, the

ICS543 can produce low skew 27 MHz and

13.5 MHz clocks. The chip has an all-chip power

down mode that stops the outputs low, and an OE

pin that tri-states the outputs.

The ICS543 is a member of the ICS

ClockBlocks™ family of clock building blocks.

See the ICS541 and ICS542 for other clock

dividers, and the ICS300, 501, 502, and 503 for

clock multipliers.

Block Diagram

Description

Features

Divider and

Selection

Circuitry

VDD GND

CLK

Output

Buffer

Output

Buffer

S1, S0

2

÷2

Input Clock

OE (both outputs)

CLK/2