ICS570A

Multiplier and Zero Delay Buffer

MDS 570A C

1

Revision 102700

Printed 11/14/00

Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com

• Packaged in 8 pin SOIC.

• Pin-for-pin replacement and upgrade to ICS570

• Functional equivalent to AV9170 (not a pin-

for-pin replacement).

• Low input to output skew of 500 ps max.

• Low skew (250 ps) outputs. One is ÷ 2 of other.

• Ability to choose between 14 different

multipliers from 0.5X to 32X.

• Input clock frequency up to 150 MHz at 3.3V.

• Can recover poor input clock duty cycle.

• Output clock duty cycle of 45/55.

• Power Down and Tri-State Mode.

• Full CMOS clock swings with 25mA drive

capability at TTL levels.

• Advanced, low power CMOS process.

• Operating voltage of 3.0 to 5.5 V.

• Industrial temperature version available

The ICS570A is a high performance Zero Delay

Buffer (ZDB) which integrates ICS’ proprietary

analog/digital Phase Locked Loop (PLL) techniques.

ICS introduced the world standard for these devices

in 1992 with the debut of the AV9170. The

designed as a performance upgrade to meet today’s

higher speed and lower voltage requirements. The

zero delay feature means that the rising edge of the

input clock aligns with the rising edges of both

outputs, giving the appearance of no delay through

the device. There are two outputs on the chip, one

being a low-skew divide by two of the other. The chip

has an all-chip power down/tri-state mode that stops

the internal PLL and puts both outputs into the high

impedance state.

The chip is ideal for synchronizing outputs in a large

variety of systems, from personal computers to data

communications to video. By allowing off-chip

feedback paths, the ICS570A can eliminate the delay

through other devices.

The ICS570A was done to improve jitter from the

original ICS570, and so it is recommended for all new

designs.

Block Diagram

Description

Features

divide by

N

Phase

Detector,

Charge

Pump, and

Loop Filter

Voltage

Controlled

Oscillator

CLK

Output

Buffer

ICLK

CLK/2

Output

Buffer

FBIN

÷2

S1, S0

2

External feedback can come from CLK or CLK/2 (see table on page 2).