ICS570A

Multiplier and Zero Delay Buffer

MDS 570A C

4

Revision 102700

Printed 11/14/00

Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com

All jitter values measured at 25 °C with 27

Ω series termination resistors and 15pF loads on both CLK and

CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left

unconnected. This will give lower output jitter.

Absolute Clock Period Jitter (ps), VDD = 3.3V

One Sigma Clock Period Jitter (ps), VDD = 5 V

One Sigma Clock Period Jitter (ps), VDD = 3.3 V

Absolute Clock Period Jitter (ps), VDD = 5 V

CLK/2

ICLK

Frequency

(MHz)

CLK/2 Frequency (MHz)

<10

±170

±210

±100

±100

±100

±80

±50

±90

<5

5 - 10

—

>10

10 - 25

>25

CLK/2

ICLK

Frequency

(MHz)

CLK Frequency (MHz)

<20

20 - 50

>50

±270

±270

±180

±220

±160

±230

±230

±230

<5

5 - 10

>10

CLK

—

ICLK

Frequency

(MHz)

CLK Frequency (MHz)

<20

20 - 50

>50

130

120

100

100

70

120

120

120

<5

5 - 10

>10

CLK

—

ICLK

Frequency

(MHz)

CLK/2 Frequency (MHz)

<10

50

60

25

35

30

20

20

25

<5

5 - 10

>10

10 - 25

>25

—

CLK/2

ICLK

Frequency

(MHz)

CLK/2 Frequency (MHz)

±1100

±500

±600

±350

±160

±90

±90

±90

<5

5 - 10

>10

<10

10 - 25

>25

—

CLK

ICLK

Frequency

(MHz)

CLK Frequency (MHz)

<20

20 - 50

>50

±850

±370

±350

±270

±140

±180

±180

±180

<5

5 - 10

>10

—

CLK

ICLK

Frequency

(MHz)

CLK Frequency (MHz)

<20

20 - 50

>50

145

100

70

65

50

85

<5

5 - 10

>10

85

85

—

CLK/2

ICLK

Frequency

(MHz)

CLK/2 Frequency (MHz)

<10

10 - 25

>25

200

135

100

70

50

20

20

20

<5

5 - 10

>10

—