ICS571

Low Phase Noise Zero Delay Buffer

MDS 571 B

3

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (Note 1)

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

DC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

DC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH, ICLK, FBIN

Pins 1, 8

VDD/2+1

VDD/2

V

Input Low Voltage, VIL, ICLK, FBIN

Pins 1, 8

VDD/2

VDD/2-1

V

Output High Voltage, VOH, CMOS level

IOH=-4mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-25mA

2.4

V

Output Low Voltage, VOL

IOL=25mA

0.4

V

IDD Operating Supply Current, 133 in, 133 out

No Load, 3.3V

34

mA

IDD Operating Supply Current, 50 in, 100 out

No Load, 3.3V

26

mA

Short Circuit Current

Each Output

±100

mA

Input Capacitance, ICLK, FBIN

5

pF

AC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

AC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

AC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

Input Frequency, clock input

FB from CLK

20

160

MHz

Input Frequency, clock input

FB from CLK/2

10

80

MHz

Skew CLK/2 with respect to CLK

Note 2

150

500

850

ps

Input clock to output connected to FBIN

Note 2

-500

500

ps

Output Clock Rise Time, 5V

0.8 to 2.0V, 15 pF load

0.3

ns

Output Clock Fall Time, 5V

2.0 to 0.8V, 15 pF load

0.4

ns

Output Clock Rise Time, 3.3V

0.8 to 2.0V, 15 pF load

0.45

ns

Output Clock Fall Time, 3.3V

2.0 to 0.8V, 15 pF load

0.55

ns

Output Clock Duty Cycle, 5V

at VDD/2

40

52 to 55

60

%

Output Clock Duty Cycle, 3.3V

at VDD/2

45

49 to 51

55

%

Absolute Clock Period Jitter, CLK, note 3

Deviation from mean

±80

ps

One Sigma Clock Period Jitter, CLK, note 3

50

ps

Phase Noise, relative to carrier

1kHz offset

-105

dBc/Hz

Phase Noise, relative to carrier

100kHz offset

-115

dBc/Hz

Notes:

1. Stresses beyond these can permanently damage the device.

2. Assumes clocks with same rise time, measured from rising edges at VDD/2. Measured with 33

Ω

termination resistors and 15 pF loads. Applies to both 3.3V and 5V operation.

3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.