ICS601-01

Low Phase Noise Clock Multiplier

MDS 601-01 G

1

Revision 090800

Printed 11/14/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

The ICS601-01 is a low cost, low phase noise, high

performance clock synthesizer for any applications

that require low phase noise and low jitter. It is

ICS’ lowest phase noise multiplier, and also the

lowest CMOS part in the industry. Using ICS’

patented analog and digital Phase Locked Loop

(PLL) techniques, the chip accepts a 10-27 MHz

crystal or clock input, and produces output clocks

up to 156 MHz at 3.3 V.

Block Diagram

Description

Features

• Packaged in 16 pin SOIC or TSSOP

• Uses fundamental 10 - 27 MHz crystal, or clock

• Patented PLL with the lowest phase noise

• Output clocks up to 156 MHz at 3.3 V

• Low phase noise: -132 dBc/Hz at 10 kHz

• Output Enable function tri states outputs

• Low jitter - 18 ps one sigma

• Full swing CMOS outputs with 25 mA drive

capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• 3.3 V or 5 V operation

Reference

Divide

Phase

Comparator

Crystal

Oscillator

ROM Based

Multipliers

VCO

Divide

Charge

Pump

Loop

Filter

VCO

Output

Buffer

X1/ICLK

X2

S0

S1

VDD

GND

OE

CLK

Output

Buffer

REFOUT

REFEN

S3 S2