ICS650-07C

Networking Clock Source

MDS 650-07C A

1

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

The ICS650-07C is a low cost, low jitter, high

performance clock synthesizer for networking

applications. Using analog Phase-Locked Loop

(PLL) techniques, the device accepts a 12.5 MHz

or 25.00 MHz clock or fundamental mode crystal

input to produce multiple output clocks for

networking chips, PCI devices, SDRAM, and

ASICs. The ICS650-07C outputs all have 0 ppm

synthesis error.

See the MK74CB214, ICS551, and ICS552-01 for

non-PLL buffer devices which produce multiple

low-skew copies of these output clocks.

See the ICS570, ICS9112-16/17/18 for zero delay

buffers that can synchronize outputs and other

needed clocks.

Block Diagram

Description

Features

• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)

• 12.5 MHz or 25.00 MHz fundamental crystal or

clock input

• Six output clocks with selectable frequencies

• SDRAM frequencies of 67, 83, 100, and 133 MHz

• Buffered crystal reference output

• Zero ppm synthesis error in all clocks

• Ideal for PMC-Sierra’s ATM switch chips

• Full CMOS output swing with 25 mA output drive

capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• 3.0V to 5.5V operating voltage

Clock

Buffer/

Crystal

Oscillator

VDD

GND

Clock Synthesis

and Control

Circuitry

12.5 MHz or

25.00 MHz

crystal or clock

Output

Buffer

CLKC1

REFOUT

2

2

Output

Buffer

CLKC2

Output

Buffer

X1

X2

Output

Buffer

CLKA1

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

ACS1,0

OE (all outputs)

÷ 2

CLKA2

Output

Buffer

Output

Buffer

CLKB1

÷ 2

CLKB2

Output

Buffer

2

BCS1,0

2

CCS