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ICS8521 数据表(PDF) 1 Page - Integrated Circuit Systems |
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ICS8521 数据表(HTML) 1 Page - Integrated Circuit Systems |
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1 / 13 page ![]() Integrated Circuit Systems, Inc. ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 8521BY www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001 1 GENERAL DESCRIPTION The ICS8521 is a low skew, 1-to-9 3.3V Differ- ential-to-LVHSTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulseson the outputs during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8521 ideal for today’s most advanced applications, such as IA64 and static RAMs. HiPerClockS™ ,&6 FEATURES • 9 LVHSTL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 500MHz • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 1.8ns (maximum) • V OH = 1.2V (maximum) • 3.3V core, 1.8V output operating supply voltages • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 32 3 1 3 0 29 28 2 7 2 6 25 9 10 1 1 12 13 14 1 5 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO ICS8521 VDD CLK nCLK CLK_SEL PCLK nPCLK GND CLK_EN CLK nCLK PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 D Q LE CLK_EN CLK_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm Package Body Y Package Top View 0 1 |
类似零件编号 - ICS8521 |
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类似说明 - ICS8521 |
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