ICS8701I datasheet(1/13 Pages) ICST

部件名	ICS8701I

功能描述	LOW SKEW 첨1, 첨2 CLOCK GENERATOR

PDF	13 Pages

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制造商	ICST [Integrated Circuit Systems]

网页	http://www.icst.com

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1 / 13 page

8701I

www.icst.com/products/hiperclocks.html

REV. A MARCH 16, 2001

1

Integrated

Circuit

Systems, Inc.

ICS8701I

LOW SKEW

¸1, ¸2

CLOCK GENERATOR

GENERAL DESCRIPTION

The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-

erator and a member of the HiPerClockS™

family of High Performance Clock Solutions

from ICS. The low impedance LVCMOS out-

puts are designed to drive 50

W series or par-

allel terminated transmission lines. The effective fanout can

be increased from 20 to 40 by utilizing the ability of the

outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output fre-

quency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The bank enable

inputs, BANK_EN0:1, support enabling and disabling each

bank of outputs individually. The master reset input, nMR/

OE, resets the internal frequency dividers and also con-

trols the active and high impedance states of all outputs.

The ICS8701I is characterized at 3.3V and mixed 3.3V in-

put supply, and 2.5V output supply operating modes. Guar-

anteed bank, output and part-to-part skew characteristics

make the ICS8701I ideal for those clock distribution appli-

cations demanding well defined performance and repeat-

ability.

FEATURES

• 20 LVCMOS outputs, 7

W typical output impedance

• Output frequency up to 250MHz

• 200ps bank skew, 250ps output skew, 300ps multiple

frequency skew, 600ps part-to-part skew

• LVCMOS / LVTTL clock input

• LVCMOS control inputs

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• 3.3V or mixed 3.3V input, 2.5V output operating

supply modes

• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm

package body, 0.5mm package lead pitch

• -40°C to 85°C ambient operating temperature

• Other divide values available on request

BLOCK DIAGRAM

PIN ASSIGNMENT

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

nMR/OE

BANK_EN0

BANK_EN1

QAO - QA4

QB0 - QB4

QC0 - QC4

QD0 - QD4

LVCMOS_CLK

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23

24

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

QC3

VDDO

QC4

QD0

VDDO

QD1

GND

QD2

GND

QD3

VDDO

QD4

QB1

VDDO

QB0

QA4

VDDO

QA3

GND

QA2

GND

QA1

VDDO

QA0

48-Pin LQFP

Y Package

Top View

ICS8701I

HiPerClockS™

,&6

1

0

¸1

¸2

1

0

1

0

1

0

Bank Enable

Logic

类似零件编号 - ICS8701I

制造商	部件名	数据表	功能描述
Integrated Circuit Syst...	ICS8701	131Kb / 15P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR REV. B AUGUST 2, 2001
	ICS8701-01	211Kb / 10P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR W/POLARITY CONTROL
	ICS8701-01Y	211Kb / 10P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR W/POLARITY CONTROL
	ICS8701-01YT	211Kb / 10P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR W/POLARITY CONTROL
Renesas Technology Corp	ICS87016AYILF	898Kb / 16P	Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator January 22, 2020

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类似说明 - ICS8701I

制造商	部件名	数据表	功能描述
Integrated Circuit Syst...	ICS8701-01	211Kb / 10P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR W/POLARITY CONTROL
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	ICS8702	221Kb / 12P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR
	ICS8737-11	127Kb / 13P	LOW SKEW 첨1/첨2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR REV. A JULY 13, 2001
Micrel Semiconductor	SY100S834	67Kb / 4P	(첨1, 첨2, 첨4) OR (첨2, 첨4, 첨8) CLOCK GENERATION CHIP
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Integrated Circuit Syst...	ICS87949-01	130Kb / 13P	LOW SKEW 첨1, 첨2 CLOCK GENERATOR REV. A JANUARY 2, 2002
Integrated Device Techn...	ICS87421I	260Kb / 14P	첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
Micrel Semiconductor	SY100S834	82Kb / 6P	(첨1, 첨2, 첨4) OR (첨2, 첨4, 첨8) CLOCK GENERATION CHIP
Micrel Semiconductor	SY100S834	249Kb / 8P	(첨1, 첨2, 첨4) or (첨2, 첨4, 첨8) Clock Generation Chip