ICS90C65 VGA Interface

The ICS90C65 has two system interfaces: System Bus and

VGA Controller, as well as other programmable inputs. Figure

1 shows how the Integrated Circuit Systems’s VGA Clock

ICS90C65 is connected to a VGA controller. Western Digital

Imaging VGA controllers normally have a status bit that indi-

cates to the VGA controller that it is working with a clock chip.

When working with a clock chip the VGA controller changes

t wo of i ts cl ock in pu ts to ou tpu ts. They

are

theVCLK1/VCSLD/VCSEL and VCLK2/VCSEL/VCSELH

outputs and they are used to select the required video frequency.

Figure 1

When the power-down capabilities are used, the control signal

for PWRDN is normally held in one of a group of latches. If

the power-down function is not to be used, PWRDN must be

in the power-down mode.

VSEL0

14.318

MHz

SD3

SD2

pull-up at reset

and PR15(5)=0

AMD(3)

VCKIN

MCLK

VCSEL

VCS

ICS90C65

WD90C26

LATCH

VSEL1

VSEL2

VCLK

MC

SELEN

CLK1

PWRDN

ICS90C65

2