2

ICS9150-08

Pin Descriptions

Notes:

1:

Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

2

REF1

OUT

14.318 MHz reference clock output

IN

Latched frequency select input. Has pull-up to VDD2.

3

REF0

OUT

14.318MHz reference clock output

PCI_STOP#

IN

Halts PCICLK (0:5) at logic "0" level when low.

(in mobile, MODE=0)

4, 10, 23, 26, 34, 42,

48, 53

GND

PWR

Ground.

5

X1

IN

14.318MHz input. Has internal load cap, (nominal 33pF).

6

X2

OUT

Crystal output. Has internal load cap (33pF) and feedback

resistor to X1

8

PCICLK_F

OUT

Free running BUS clock not afected by PCI_STOP#

IN

Latched input for MODE select. Converts pin 3 to PCI_STOP# when

low for power management.

9, 11, 12,

13, 14, 16

PCICLK (0:5)

OUT

PCI Clock Outputs.

17

BUFFERIN

IN

Input for Buffers

27

SDATA

IN

28

SCLK

IN

30

24MHz

OUT

24MHz clock output for Super I/O or FD.

IN

Latched frequency select input. Has pull-up to VDD4.

29

48MHz

OUT

48MHz clock output for USB.

IN

Latched frequency select input. Has pull-up to VDD2.

1, 7, 15, 20,

31, 37, 45

VDD2, VDD1,

VDD3, VDD4

PWR

Nominal 3.3V power supply, see power groups for function.

18, 19, 21, 22, 24,

25, 32, 33, 35, 36,

38, 39, 40 41, 43,

44, 46

SDRAM

(1:8) (15:12) (7:0), 16

OUT

SDRAM clocks

47

CPU_STOP#

IN

Halts CPUCLK (1:2), IOAPIC0, SDRAM (0:16) clocks at logic "0"

level when low.

50, 56

VDDL2, VDDL1

PWR

CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V

nominal.

55

IOAPIC0

OUT

IOAPIC clock output. (14.318 MHz) Poweredby VDDL1

51, 49

CPUCLK (1:2)

OUT

CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)

52

CPUCLK_F

OUT

Free running CPU output clock. Not affected ty the CPU_STOP#.

54

IOAPIC_F

OUT

Freerunning IOAPIC clock output. Not affected by the CPU_STOP#

(14.31818 MHz) Powered by VDDL1