2

ICS9159-07

Pin Descriptions

28-Pin SOIC

Pin Configuration

*

Internally pulled-up.

**

External pull-up resistor of 5 to 20 kW recommended due to dynamic coupling of adjacent CPU pins.

*** Ground for bus clock buffers.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1X1

IN

XTAL or external reference frequency input. This input includes XTAL load

capacitance and feedback bias for a 12 - 16 MHz XTAL. Normally, 14.318 MHz.

2

X2

OUT

XTAL output which includes XTAL load capacitance.

6,7, 9

CPU(0:2)

OUT

Processor clock outputs which are a multiple of the input reference frequency as

shown in the table below.

3, 11, 23

GND

PWR

Device Ground.

4, 5, 14

FS(0:2)

IN

Frequency multiplier select pins. See table below. These inputs have internal pull-

up devices.*

8, 26

VDD

PWR

Positive power supply.

10

OE

IN

Output Enable. All outputs tristate when low.**

12

DOZE#

IN

Reduces CPU clock frequency to 10 MHz when at a logic low level.*

13

BSEL#

IN

Synchronous and non-synchronous bus clock selector.* ASYNC=0, SYNC=1

15, 16, 18 19,

21, 22, 27

BCLK(0:6)

OUT

Bus clock outputs are fixed at 2 ¤3 the PCLK frequency.

20

PWR

Power for BUS output buffers.

17

GNDB

PWR

This ground return path is brought on separately to permit separating the noise

impulses from high output buffers from affecting sensitive internal circuitry.***

24

DISK

OUT

Fixed 24 MHz clock (with 14.318 MHz input).

25

KEYBD

OUT

Fixed 12 MHz clock (with 14.318 MHz input).

28

REF

OUT

REF is a buffered copy of the crystal oscillator or reference input clock,

nominally 14.31818 MHz.