2

ICS9159-12

Pin Descriptions

Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU

and fixed frequencies (Pins 1, 8 and 26) are being supplied with 3 volts.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

8, 25

VDD

PWR

Power for logic, CPU and fixed frequency output buffers.

1X1

IN

XTAL or external reference frequency input. This input includes XTAL load

capacitance and feedback bias for a 10 - 30 MHz XTAL.

2

X2

OUT

XTAL output which includes XTAL load capacitance.

3

OEN

IN

OEN tristates all outputs when low. This input has an internal pull-up device.

4

BPIN

IN

Input to BPIN(0:5) buffers.

5

BHIN

IN

Input to BHIN(0:3) buffers.

11, 23

GND

PWR

Ground for logic, CPU and fixed frequency output buffers.

6, 7, 9, 10

BH(0:3)

OUT

Buffered copies of the BHIN input, typically used to drive the PCI device clock

inputs at one half the CPU frequency.

13, 12

FS(0:1)

IN

Frequency multiplier select pins. See table below. These inputs have internal pull-up

devices.

14, 20

VDD

PWR

Power for BCLK output buffers.

15, 16, 18 19,

21, 22

BP(0:5)

OUT

Buffered copies of the BPIN input, typically used to drive the host device clock

inputs at the CPU frequency. 17 VSS PWR Ground for BCLK output buffers.

24

CPU

OUT

The CPU output, which is a multiple of the input reference frequency as shown in

the table above. Duty cycle is 50/50±5% with a maximum frequency of 100 MHz.

26

24M

OUT

The 24M clock is fixed at 24 MHz.

28, 27

REF(0:1)

OUT

REF is a buffered copy of the crystal oscillator or reference input clock,

nominally 14.31818 MHz.