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ICS9159-13 数据表(PDF) 6 Page - Integrated Circuit Systems

部件名 ICS9159-13
功能描述  Frequency Generator and Integrated Buffer for PENTIUM
PDF  7 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS9159-13 数据表(HTML) 6 Page - Integrated Circuit Systems

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ICS9159-13
Electrical Characteristics at 5.5V
VDD = 4.5 – 5.5 V, TA = 0 – 70
° C
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time1
Tr1
20pF load, 0.8 to 2.0V PCLK & BCLK
-
0.55
0.95
ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V PCLK & BCLK
-
0.52
0.90
ns
Rise Time
1
Tr2
20pF load, 20% to 80% PCLK & BCLK
-
1.2
2.1
ns
Fall Time
1
Tf2
20pF load, 80% to 20% PCLK & BCLK
-
1.1
2.0
ns
Duty Cycle
1
Dt1
20pF load @ VOUT=1.4V
52
57
62
%
Duty Cycle
1
Dt2
20pF load @ VOUT=50%
45
50
55
%
Jitter, One Sigma
1
Tj1s1
PCLK & BCLK Clocks; Load=20pF,
RS=33W FOUT>25 MHz
-50
150
ps
Jitter, Absolute
1
Tjab1
PCLK & BCLK Clocks; Load=20pF,
RS=33W FOUT>25 MHz
-250
-
250
ps
Jitter, One Sigma
1
Tj1s2
REF CLKs; Load=20pF RS=33W
-
1
3
%
Jitter, Absolute
1
Tjab2
REF CLKs; Load=20pF RS=33W
-5
2
5
%
Input Frequency
1
Fi
12.0
14.318
16.0
MHz
Logic Input Capacitance
1
CIN
Logic input pins
-
5
-
pF
Crystal OscillatorCapacitance
1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time1
ton
From VDD=1.6V to 1 st crossing of 66.5
MHz VDD supply ramp < 40ms
-2.5
4.5
ms
Frequency Settling Time
1
ts
From 1st crossing of acquisition to < 1%
settling
-2.0
4.0
ms
Clock Skew Window
1
Tsk1
PCLK to PCLK; Load=20pF; @1.4V
-
150
250
ps
Clock Skew Window
1
Tsk2
BCLK to BCLK; Load=20pF; @1.4V
-
300
500
ps
Clock Skew Window1
Tsk3
PCLK to BCLK; Load=20pF; @1.4V
-
400
600
ps



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