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ICS9248-96 数据表(PDF) 8 Page - Integrated Circuit Systems |
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ICS9248-96 数据表(HTML) 8 Page - Integrated Circuit Systems |
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8 / 12 page  8 ICS9248-96 0311D—04/23/04 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table Group Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps PCI to PCI 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns USB & DOT Async N/A Async N/A Async N/A CPU 133MHz CPU 66MHz CPU 100MHz Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2VDD + 0.3 V Input Low Voltage VIL VSS - 0.3 0.8 V Input High Current IIH VIN = VDD -5 5 mA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 IDD3.3OP 300 340 IDD2.5OP 12 15 IDD3.3OP 300 350 IDD2.5OP 25 30 IDD3.3OP 300 420 IDD2.5OP 35 40 Input Frequency Fi VDD = 3.3 V 14.31818 MHz CIN Logic Inputs 5pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 27 45 pF Transition time 1 Ttrans To 1st crossing of target frequency 3 ms Settling time 1 Ts From 1st crossing to 1% target frequency 3 ms Clk Stabilization 1 TSTAB From VDD = 3.3 V to 1% target frequency 3ms 1Guaranteed by design, not 100% tested in production. 300 IDD3.3PD CL = Max loads; VIN = VDD or GND Input Capacitance 1 Input Low Current Power Down Supply Current CL = Max loads; CPU @ 66 MHz; SDRAM @ 100 MHz CL = Max loads; CPU @ 100 MHz; SDRAM @ 100 MHz CL = Max loads; CPU @ 133 MHz; SDRAM @ 133 MHz Operating Supply Current 600 mA µA mA mA mA |
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