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IDT29FCT520CSOB 数据表(PDF) 2 Page - Integrated Device Technology |
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IDT29FCT520CSOB 数据表(HTML) 2 Page - Integrated Device Technology |
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2 / 8 page ![]() 7.2 2 IDT29FCT520A/B/C MULTILEVEL PIPELINE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS 2620 drw 02 5 6 7 8 9 10 11 L28-1 25 24 23 22 21 20 19 INDEX D1 D2 D3 D4 D5 D6 NC NC Y0 Y1 Y2 Y3 Y4 Y5 12 13 14 15 16 17 18 43 2 1 28 27 26 DIP/CERPACK/SOIC TOP VIEW 5 6 7 8 9 10 11 12 GND 1 2 3 4 24 23 22 21 20 19 18 17 Vcc 16 15 14 13 P24-1, D24-1, E24-1 & SO24-2 S0 S1 Y0 Y1 Y2 Y3 Y4 Y5 OE I0 I1 D0 D1 D2 D3 D4 D5 D6 D7 CLK Y6 Y7 LCC TOP VIEW DEFINITION OF FUNCTIONAL TERMS Pin Names Description Dn Register input port. CLK Clock input. Enter data into registers on LOW- to-HIGH transitions. I0, I1 Instruction inputs. See Figure 1 and In- struction Control Tables. S0, S1 Multiplexer select. Inputs either register A1, A2, B1 or B2 data to be available at the output port. OE Output enable for 3-state output port Yn Register output port. 2620 tbl 01 REGISTER SELECTION S1 S0 Register 00 B2 01 B1 10 A2 11 A1 2620 tbl 02 |
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