5.2

7

IDT6167SA/LA

CMOS STATIC RAM 16K (16K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (

WE

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

CS

NOTES:

1.

WE or CS must be inactive during all address transitions.

2. A write occurs during the overlap of a LOW

CS and a LOW WE.

CS or WE going HIGH to the end of the write cycle.

4. If the

CS low transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

5. Transition is measured

±200mV from steady state.

6. During this period, the I/O pins are in the output state and the input signals must not be applied.

CS

2981 drw 08

ADDRESS

WE

(5)

(6)

(3)

(5)

(5)

t

CS

2981 drw 09

ADDRESS

WE

(3)