AD9501 datasheet(2/12 Pages) AD

2 / 12 page

REV. B

–2–

AD9501–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

0 C to 70 C

Test

AD9501JN/JP

Parameter

Temp

Level

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

Differential Nonlinearity

∞CI

0.5

LSB

Integral Nonlinearity

∞CI

LSB

Monotonicity

∞CI

Guaranteed

DIGITAL INPUTS

Latch Input 1 Voltage

Full

2.0

Latch Input 0 Voltage

Full

0.8

Logic 1 Voltage

Full

2.0

Logic 0 Voltage

Full

0.8

Logic 1 Current

Full

Logic 0 Current

Full

Digital Input Capacitance

∞CIV

5.5

Data Setup Time (tS)

∞CV

2.5

Data Hold Time (tH)

∞CV

2.5

Latch Pulse Width (tL)25

∞CV

3.5

Reset/Trigger Pulse Width (tR, tT)25

∞CV

DYNAMIC PERFORMANCE

Maximum Trigger Rate

∞CIV

MHz

Minimum Propagation Delay (tPD)

∞CI

Propagation Delay Tempco

Full

ps/

∞C

Full-Scale Range Tempco

Full

ps/

∞C

Delay Uncertainty

∞CV

Reset Propagation Delay (tRD)

∞CI

14.5

17.5

Reset-to-Trigger Holdoff (tTHO)

∞CV

4.5

Trigger-to-Reset Holdoff (tRHO)

∞CV

Minimum Output Pulse Width

∞CV

7.5

Output Rise Time

∞CI

2.3

3.5

Output Fall Time

∞CI

1.0

2.0

DAC Settling Time (tLD)

∞CV

Linear Ramp Settling Time (tLRS)

∞CV

DIGITAL OUTPUT

Logic 1 Voltage (Source 1 mA)

Full

2.4

Logic 0 Voltage (Sink 4 mA)

Full

0.24

0.4

POWER SUPPLY

Positive Supply Current (5.0 V)

Full

69.5

Power Dissipation

Full

415

Power Supply Rejection Ratio

Full-Scale Range Sensitivity

∞CI

0.7

2.0

ns/V

Minimum Prop Delay Sensitivity

∞CI

0.45

1.7

ns/V

NOTES

11Digital data inputs must remain stable for the specified time prior to the positive transition of the LATCH signal.

12Digital data inputs must remain stable for the specified time after the positive transition of the LATCH signal.

13Programmed delay (t

D) = 0 ns. Maximum self-resetting trigger rate is limited to 6.9 MHz with 100 ns programmed delay. If tD = 0 ns and external RESET signal is

used, maximum trigger rate is 23 MHz.

14Programmed delay (t

D) = 0 ns. In operation, any programmed delays are in addition to the minimum propagation delay (tPD).

15Programmed delay (t

D) = 0 ns. Minimum propagation delay (tPD).

16Measured from 50% transition point of the RESET signal input to the 50% transition point of the falling edge of the output.

17Minimum time from the falling edge of RESET to the triggering input to ensure valid output pulse, using external RESET pulse.

18Minimum time from triggering event to rising edge of RESET to ensure valid output event, using external RESET pulse. Extends to 125 ns when programmed delay

is 100 ns.

19When self-resetting with a full-scale programmed delay.

10Measured from 0.4 V to 2.4 V; source = 1 mA; sink = 4 mA.

11Measured from the data input to the time when the AD9501 becomes 8-bit accurate, after a full-scale change in the program delay data word.

12Measured from the RESET input to the time when the AD9501 becomes 8-bit accurate, after a full-scale programmed delay.

13Supply voltage should remain stable within

±5% for normal operation.

14Measured at +V

S = 5.0 V

± 5%; specification shown is for worst case.

Specifications subject to change without notice.

(+VS = 5 V; CEXT = Open; RSET = 3090

[Full-Scale Range = 100 ns]; Pin 8 grounded

and device output connected to Pin 4 RESET input, unless otherwise noted.)

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