IDT7132LA55P datasheet(5/11 Pages) IDT

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6.02

IDT7132SA/LA AND IDT7142SA/LA

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)

7132X20

(2)

7132X25

(5)

7132X35

7132X55

7132X100

7142X25

(5)

7142X35

7142X55

7142X100

Symbol

Parameter

Min. Max.

Min. Max. Min.

Max. Min. Max. Min.

Max. Unit

Read Cycle

tRC

Read Cycle Time

—

100

—

tAA

Address Access Time

—

100

tACE

Chip Enable Access Time

—

100

tAOE

Output Enable Access Time

—

tOH

Output Hold From Address Change

—

tLZ

Output Low-Z Time

(1,4)

0—

—

tHZ

Output High-Z Time

(1,4)

—

tPU

Chip Enable to Power Up Time

(4)

0—

—

tPD

Chip Disable to Power Down Time(4)

—

NOTES:

2689 tbl 08

1. Transition is measured

±500mV from Low or High-impedance voltage Output Test Load (Figure 2).

2. Com'l Only, 0

°C to +70°C temperature range. PLCC package only.

3. “X” in part numbers indicates power rating (SA or LA).

4. This parameter is guaranteed by device characterization, but is not production tested.

5. Not available in DIP packages.

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

(1)

NOTES:

1. R/

W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.

2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read

operations,

BUSY has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

ADDRESS

DATAOUT

tRC

tOH

PREVIOUS DATA VALID

tAA

tOH

DATA VALID

2692 drw 07

tBDDH (2,3)

BUSYOUT

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