IDT7142LA55P datasheet(9/11 Pages) IDT

9 / 11 page

6.02

IDT7132SA/LA AND IDT7142SA/LA

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

BUSYR

2692 drw 12

tWP

tWH

tWB

(2)

(1)

TIMING WAVEFORM OF WRITE WITH

BUSY

BUSY(3)

NOTES:

1. tWH must be met for both

BUSY Input (IDT7142, slave) or Output (IDT7132, master).

BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.

3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

CE TIMING (1)

tAPS

ADDR

'A'

and 'B'

ADDRESSES MATCH

tBAC

tBDC

CE'B'

CE'A'

BUSY'A'

2692 drw 13

(2)

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)

BUSY'B'

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

tAPS

ADDR'A'

ADDR'B'

2692 drw 14

(2)

tBAA

tBDA

tRC or tWC

NOTES:

1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.

2. If tAPS is not satisified, the

BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).

IDT7142LA55P 数据表(PDF) 9 Page - Integrated Device Technology

IDT7142LA55P 数据表(HTML) 9 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11

数据表下载