IDT7130LA55J datasheet(8/14 Pages) IDT

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IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

CE CONTROLLED TIMING)(1,5)

NOTES:

1. R/

W or CE must be High during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of

CE = VIL and R/W = VIL.

3. tWR is measured from the earlier of

CE or R/W going High to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the

CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state

with the Output Test Load (Figure 2).

8. If

OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off

and data to be placed on the bus for the required tDW. If

OE is High during a R/W controlled write cycle, this requirement does not apply and

the write pulse can be as short as the specified tWP.

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/

W CONTROLLED TIMING)(1,5,8)

tWC

ADDRESS

DATA OUT

DATA IN

tAS

tOW

tDW

tDH

tAW

tWP(2)

tHZ

(4)

tWZ

tHZ

2689 drw 10

(6)

(7)

(3)

(7)

tWR

tWC

ADDRESS

DATA IN

tAS

tEW

tWR

tDW

tDH

tAW

2689 drw 11

(6)

(2)

(3)

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