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IDT7134LA55F 数据表(PDF) 2 Page - Integrated Device Technology |
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IDT7134LA55F 数据表(HTML) 2 Page - Integrated Device Technology |
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2 / 9 page  6.04 2 IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS(1,2) NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of actual part-marking. A10R 2720 drw 02 I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R A9R A8R A7R A6R A4R A3R A2R A1R A0R 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 148 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L IDT7134 P48–1 & C48–2 DIP TOP VIEW (3) CEL R/ WL OEL VCC A5R R OE A11R R/ WR CER A11L A10L GND 2720 drw 04 IDT7134 L48-1 & F48-1 LCC/Flatpack TOP VIEW (3) INDEX 65 43 2 1 48 47 46 45 44 43 19 20 21 22 23 25 26 27 28 29 30 24 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O6R I/O7R 42 41 40 39 38 37 36 35 34 33 32 31 7 8 9 10 11 12 13 14 15 16 17 18 2720 drw 03 IDT7134 J52-1 PLCC TOP VIEW (3) INDEX OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R 46 45 44 43 42 41 40 39 38 37 36 35 34 I/O3L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 49 50 51 52 1 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 24 23 22 21 ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Com’l. Mil. Unit VTERM (2) Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V with Respect to Ground TA Operating 0 to +70 –55 to +125 °C Temperature TBIAS Temperature –55 to +125 –65 to +135 °C Under Bias TSTG Storage –55 to +125 –65 to +150 °C Temperature PT (3) Power Dissipation 1.5 1.5 W IOUT DC Output Current 50 50 mA 2720 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or 10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +0.5V. CAPACITANCE(1) (TA = +25 °C, f = 1.0MHz) Symbol Parameter Conditions(2) Max. Unit CIN Input Capacitance VIN = 3dv 11 pF COUT Output Capacitance VOUT = 3dv 11 pF 2720 tbl 02 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V and from 3V to 0V. |
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