IDT7130LA55F datasheet(7/14 Pages) IDT

7 / 14 page

6.01

IDT7130SA/LA AND IDT7140SA/LA

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(3)

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)

7130X20(2)

7130X25(6)

7130X35

7130X55

7130X100

7140X25(6)

7140X35

7140X55

7140X100

Symbol

Parameter

Min.

Max.

Min. Max.

Min.

Max. Min.

Max.

Min.

Max.

Unit

Write Cycle

tWC

Write Cycle Time(3)

—

100

—

tEW

Chip Enable to End-of-Write

—

tAW

Address Valid to End-of-Write

—

tAS

Address Set-up Time

—

tWP

Write Pulse Width(4)

—

tWR

Write Recovery Time

—

tDW

Data Valid to End-of-Write

—

tHZ

Output High-Z Time

(1)

—10

—

—15

—

tDH

Data Hold Time

—

tWZ

Write Enabled to Output in High-Z

(1)

—10

—

—15

—

tOW

Output Active From End-of-Write(1)

0—

—

NOTES:

2689 tbl 10

1. Transition is measured

±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by

device characterization but is not production tested.

2. 0

°C to +70°C temperature range only, PLCC and TQFP packages.

3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/

W = VIL must occur after tBAA.

4. If

OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off

data to be placed on the bus for the required tDW. If

OE is High during a R/W controlled write cycle, this requirement does not apply and the

write pulse can be as short as the specified tWP.

5. “X” in part numbers indicates power rating (SA or LA).

6. Not available in DIP packages.

tACE

tAOE

tHZ

tLZ

tPD

VALID DATA

tPU

50%

DATAOUT

CURRENT

ICC

ISS

50%

2689 drw 09

(4)

(1)

(2)

(4)

tLZ

tHZ

NOTES:

1. Timing depends on which signal is asserted last,

OE or CE.

2. Timing depends on which signal is deaserted first,

OE or CE.

3. R/

W = VIH and the address is valid prior to or coincidental with CE transition Low.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

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