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IDT74FST163232 数据表(PDF) 5 Page - Integrated Device Technology |
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IDT74FST163232 数据表(HTML) 5 Page - Integrated Device Technology |
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5 / 6 page ![]() IDT74FST163232 16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH COMMERCIAL TEMPERATURE RANGE 5 TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION Pulse Generator R T D.U.T. VCC VIN C L VOUT 50pF 500 Ω 500 Ω 7.0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 3V 1.5V 0V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 3V 1.5V 0V tPLH tPHL tPHL VOL CONTROL INPUT 3V 1.5V 0V 3.5V 0V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZ tPZL tPZH tPHZ 3.5V 0V 1.5V 1.5V ENABLE DISABLE VOH PRESET CLEAR CLOCK ENABLE ETC. ENABLE AND DISABLE TIMES PROPAGATION DELAY PULSE WIDTH SET-UP, HOLD AND RELEASE TIMES Test Switch Disable Low Enable Low Closed All Other Tests Open Open Drain DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator. NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 3511 lnk 04 3511 lnk 03 3511 lnk 05 3511 lnk 06 3511 lnk 07 3511 lnk 08 |
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