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IDT7132LA55F 数据表(PDF) 9 Page - Integrated Device Technology |
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IDT7132LA55F 数据表(HTML) 9 Page - Integrated Device Technology |
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9 / 16 page  6.42 IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges 9 AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(5,6) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. PLCC package only. 3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. 'X' in part numbers indicates power rating (SA or LA). 6. Industrial temperature: for specific speeds, packages and powers contact your sales office. Symbol Parameter 7132X20(2) 7142X20(2) Com'l Only 7132X25(2) 7142X25(2) Com'l, Ind & Military 7132X35 7142X35 Com'l & Military Unit Min. Max. Min. Max. Min. Max. WRITE CYCLE tWC Write Cycle Time(3) 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width(4) 15 ____ 15 ____ 25 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 12 ____ 15 ____ ns tHZ Output High-Z Time(1) ____ 10 ____ 10 ____ 15 ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1) ____ 10 ____ 10 ____ 15 ns tOW Output Active from End-of-Write(1) 0 ____ 0 ____ 0 ____ ns 2692 tbl 09 Symbol Parameter 7132X55 7142X55 Com'l & Military 7132X100 7142X100 Com'l & Military Unit Min. Max. Min. Max. WRITE CYCLE tWC Write Cycle Time(3) 55 ____ 100 ____ ns tEW Chip Enable to End-of-Write 40 ____ 90 ____ ns tAW Address Valid to End-of-Write 40 ____ 90 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width(4) 30 ____ 55 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 20 ____ 40 ____ ns tHZ Output High-Z Time(1) ____ 25 ____ 40 ns tDH Data Hold Time 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1) ____ 30 ____ 40 ns tOW Output Active from End-of-Write(1) 0 ____ 0 ____ ns 2692 tbl 10 |
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