IMP708R/S/T/J RESET reset outputs no longer pull down; it

becomes indeterminate. To avoid the possibility that stray charges

could build up and force RESET to the wrong state, a pull-down

resistor should be connected to the RESET pin, thus draining such

charges to ground. The resistor value is not critical. A 100k

Ω resis-

tor will pull RESET to ground without loading it.

Power Fail circuitry. If a resistive divider is connected from the

voltage to be monitored to the PFI input, the PFO (output) will go

LOW if the divider voltage goes below its 1.25V reference. Should

hysteresis be desired, connect a resistor (equal to approximately

10 times the sum of the two resistors in the divider) between the

PFI and PFO pins. A capacitor between PFI and GND will reduce

circuit sensitivity to input high frequency noise. If it is desired to

assert a reset in addition to the PFO flag, this may be achieved by

connecting the PFO output to MR.

IMP706P/R/S/T/J, IMP708R/S/T/J

IMP706P/R/S/T/J, IMP708R/S/T/J

©

1999 IMP, Inc.

408-432-9100/www.impweb.com

7

Bi-directional Reset Pin Interfacing

The IMP706/8 can interface with

µP/µC bi-directional reset pins

by connecting a 4.7k

Ω resistor in series with the RESET output

and the

µP/µC bi-directional reset pin.

Supply

Voltage

IMP70x

GND

GND

RESET

4.7k

W

706P_06.eps

Bi-directional I/O Pin

(Example: 68HC11)

BUF

Buffered

RESET

mC or mP

RESET

Input

Application Information

e

b

D

E1 E

a

L

C

0.10mm

0.004in

A1

A2

A

MicroSO (8-Pin).eps

MicroSO (8-Pin)

Package Dimensions

s

e

h

c

n

Is

r

e

t

e

m

i

ll

i

M

n

i

Mx

a

Mn

i

Mx

a

M

*

)

n

i

P

-

8

(

O

S

o

r

c

i

M

A

–

–

–

–

–

3

3

4

0

.

0

–

–

–

–

0

1

.

1

1

A0

2

0

0

.

09

5

0

0

.

00

5

0

.

05

1

.

0

2

A5

9

2

0

.

04

7

3

0

.

05

7

.

05

9

.

0

b8

9

0

0

.

07

5

1

0

.

05

2

.

00

4

.

0

C1

5

0

0

.

01

9

0

0

.

03

1

.

03

2

.

0

D2

4

1

1

.

00

2

2

1

.

00

9

.

20

1

.

3

eC

S

B

6

5

2

0

.

0C

S

B

5

6

.

0

EC

S

B

3

9

1

.

0C

S

B

0

9

.

4

1

E2

4

1

1

.

00

2

2

1

.

00

9

.

20

1

.

3

L7

5

1

0

.

06

7

2

0

.

00

4

.

00

7

.

0

a

°

0

°

6

°

0

°

6

3

t

a

.

a

2

0

t

_

P

6

0

7

* JEDEC Drawing MO-187AA