IDT54FCT240CSO datasheet(7/8 Pages) IDT

7 / 8 page

IDT54/74FCT240/241/244/540/541/A/C

FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.8

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

Pulse

Generator

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

1.5V

t SU

t H

t REM

t SU

R T

D.U.T.

VCC

VIN

C L

V OUT

50pF

500

Ω

500

Ω

7.0V

SAME PHASE

INPUT TRANSITION

1.5V

VOH

VOL

tPLH

t PHL

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

CONTROL

INPUT

1.5V

3.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

V OL

V OH

1.5V

t PLH

tPHL

0.3V

tPLZ

tPZL

tPZH

tPHZ

3.5V

1.5V

ENABLE

DISABLE

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

t W

1.5V

NOTES

2606 drw 10

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate

≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;

≤ 2.5ns.

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

Closed

Enable Low

All Other Tests

Open

DEFINITIONS:

2606 tbl 10

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

IDT54FCT240CSO 数据表(PDF) 7 Page - Integrated Device Technology

IDT54FCT240CSO 数据表(HTML) 7 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8

数据表下载

链接网址

IDT54FCT240CSO 数据表(PDF) 7 Page - Integrated Device Technology

IDT54FCT240CSO 数据表(HTML) 7 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8

数据表 下载

链接网址

数据表下载