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IDT7142LA55PI 数据表(PDF) 7 Page - Integrated Device Technology

部件名 IDT7142LA55PI
功能描述  HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

IDT7142LA55PI 数据表(HTML) 7 Page - Integrated Device Technology

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6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,5)
NOTES:
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).
2. PLCC package only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20(2)
7142X20(2)
Com'l Only
7132X25(2)
7142X25(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Unit
Symbol
Parameter
Min.Max.Min.Max.Min.Max.
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
ns
tAA
Address Access Time
____
20
____
25
____
35
ns
tACE
Chip Enable Access Time
____
20
____
25
____
35
ns
tAOE
Output Enable Access Time
____
11
____
12
____
20
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time(1,4)
0
____
0
____
0
____
ns
tHZ
Output High-Z Time(1,4)
____
10
____
10
____
15
ns
tPU
Chip Enable to Power Up Time(4)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(4)
____
20
____
25
____
35
ns
2692 tbl 08a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
55
____
100
____
ns
tAA
Address Access Time
____
55
____
100
ns
tACE
Chip Enable Access Time
____
55
____
100
ns
tAOE
Output Enable Access Time
____
25
____
40
ns
tOH
Output Hold from Address Change
3
____
10
____
ns
tLZ
Output Low-Z Time(1,4)
5
____
5
____
ns
tHZ
Output High-Z Time(1,4)
____
25
____
40
ns
tPU
Chip Enable to Power Up Time(4)
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(4)
____
50
____
50
ns
2692 tbl 08b



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