Data Sheet

AD5231

Rev. D | Page 13 of 28

TEST CIRCUITS

Figure 26 to Figure 35 define the test conditions used in the specifications.

A

W

B

NC

DUT

NC = NO CONNECT

Figure 26. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

A

W

B

DUT

V+

Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL)

A

W

B

DUT

Figure 28. Wiper Resistance

A

W

B

V+

PSRR (dB) = 20 log

PSS (%/%) =

Figure 29. Power Supply Sensitivity (PSS, PSRR)

OFFSET BIAS

OFFSET

GND

A

B

DUT

W

5V

OP279

Figure 30. Inverting Gain

OFFSET BIAS

OFFSET

GND

A

B

DUT

W

5V

OP279

Figure 31. Noninverting Gain

OFFSET

GND

A

B

DUT

W

+15V

OP42

–15V

+2.5V

Figure 32. Gain vs. Frequency

+

–

DUT

NC

CODE = 0x000

0.1V

0.1V

W

B

A

NC = NO CONNECT

Figure 33. Incremental On Resistance

W

B

DUT

NC

NC

GND

A

NC = NO CONNECT

Figure 34. Common-Mode Leakage Current

200µA

200µA

OR

TO OUTPUT

PIN

50pF