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Data Sheet

AD5259

Rev. C | Page 5 of 24

TIMING CHARACTERISTICS

VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

I2C INTERFACE TIMING

CHARACTERISTICS1

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time Between Stop

and Start

1.3

μs

tHD;STA Hold Time (Repeated Start)

After this period, the first clock pulse is

generated.

0.6

μs

tLOW Low Period of SCL Clock

1.3

μs

tHIGH High Period of SCL Clock

0.6

μs

tSU;STA Setup Time for Repeated

Start Condition

0.6

μs

tHD;DAT Data Hold Time

0.9

μs

tSU;DAT Data Setup Time

100

tF Fall Time of Both SDA and

SCL Signals

300

tR Rise Time of Both SDA and

SCL Signals

300

tSU;STO Setup Time for Stop Condition

t10

0.6

μs

EEPROM Data Storing Time

tEEMEM_STORE

EEPROM Data Restoring Time at

Power On2

tEEMEM_RESTORE1

VDD rise time dependent. Measure without

decoupling capacitors at VDD and GND.

300

μs

EEPROM Data Restoring Time upon

Restore Command2

tEEMEM_RESTORE2

VDD = 5 V.

300

μs

EEPROM Data Rewritable Time3

tEEMEM_REWRITE

540

μs

FLASH/EE MEMORY RELIABILITY

Endurance4

100

700

kCycles

Data Retention5

100

Years

1 Standard I2C mode operation guaranteed by design.

2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.

3 Delay time after power-on PRESET prior to writing new EEPROM data.

4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.

5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

t10

SCL

SDA

Figure 4. I2C Interface Timing Diagram

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