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83C51KB 数据表(PDF) 13 Page - Intel Corporation

部件名 83C51KB
功能描述  HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
PDF  19 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

83C51KB 数据表(HTML) 13 Page - Intel Corporation

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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.1 D.C. Characteristics
Table 7. D.C. Characteristics
Symbol
Parameter
Min
Typical
(note 1)
Max
Unit
Test
Condition
VIL
Input Low Voltage (except
EA#, RCIN, RST)
-0.5
0.2 VCC -0.1
V
VIL1
Input Low Voltage RST
0
0.2 VCC -0.3
V
VIL2
Input Low Voltage EA#
-0.5
0.5
V
VIL3
Input Low Voltage RCIN
VCC/3
V
VIH
Input High Voltage (except
EA#, RCIN, RST)
0.2VCC+
0.9
VCC+0.5
V
VIH1
Input High Voltage (EA#,
RST)
0.7VCC
VCC+0.5
V
VIH2
Input High Voltage RCIN
2VCC/3
IIH = 8 mA
when external
clock source is
used on RCIN
VOL
Output Low Voltage (Port 0, 1,
2, 3, ALE, PSEN# except
P3.4/LED0, P3.5/LED1,
P3.6/LED2, P3.7/LED3)
0.3
0.45
1.0
VIOL=200 µA
IOL=3.2 mA
IOL=7.0 mA
(note 2,3)
IOL
Output Low Current
(P3.4/LED0, P3.5/LED1,
P3.6/LED2, P3.7/LED3 only)
613
22
mA
VOL=3.0 V
VOH
Output High Voltage (Port 0,
1, 2, 3, ALE, PSEN#, except
P3.0, P3.2, P3.3)
VCC-0.3
VCC-0.7
VCC-1.5
VIOH= -25 µA
IOH= -65 µA
IOH= -100 µA
(note 4)
NOTE:
1.
Typical values are obtained using VCC=5.0V, TA=25°C and are not guaranteed.
2.
Under steady state (non-transient) conditions, IOL must be externally limited as follow:
Maximum IOL per Port Pin—Port 0, 1, 2, P3.1-P3.3:
10mA
Maximum IOL per Port Pin—P3.4-P3.7:
22mA
Maximum IOL per 8-bit port—Port 0-2:
15mA
Ports 3:
95mA
Maximum Total IOL for AllOutput Pins:
110mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3.
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance dis-
charging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where
capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
4.
Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC
specification when the address lines are stabilizing.



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