CS80C88 datasheet(13/32 Pages) INTERSIL

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3-13

Basic System Timing

In minimum mode, the MN/MX pin is strapped to VCC and

the processor emits bus control signals (RD, WR, IO/M, etc.)

directly. In maximum mode, the MN/MX pin is strapped to

GND and the processor emits coded status information

which

the

82C88

bus

controller

uses

generate

MULTIBUS

™ compatible bus control signals.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the

address latch enable (ALE) signal (see Figure 5). The trail-

ing (low going) edge of this signal is used to latch the

address information, which is valid on the address data bus

(ADO-AD7) at this time, into the 82C82/82C83 latch.

Address lines A8 through A15 do not need to be latched

because they remain valid throughout the bus cycle. From

T1 to T4 the IO/M signal indicates a memory or I/O opera-

tion. At T2 the address is removed from the address data

bus and the bus is held at the last valid logic state by internal

bus-hold devices. The read control signal is also asserted at

T2. The read (RD) signal causes the addressed device to

enable its data bus drivers to the local bus. Some time later,

valid data will be available on the bus and the addressed

device will drive the READY line HIGH. When the processor

returns the read signal to a HIGH level, the addressed

device will again three-state its bus drivers. If a transceiver

(82C86/82C87) is required to buffer the local bus, signals

DT/R and DEN are provided by the 80C88.

A write cycle also begins with the assertion of ALE and the

emission of the address. The IO/M signal is again asserted

to indicate a memory or I/O write operation. In T2, immedi-

ately following the address emission, the processor emits

the data to be written into the addressed location. This data

remains valid until at least the middle of T4. During T2, T3,

and Tw, the processor asserts the write control signal. The

write (WR) signal becomes active at the beginning of T2, as

opposed to the read, which is delayed somewhat into T2 to

provide time for output drivers to become inactive.

The basic difference between the interrupt acknowledge

cycle and a read cycle is that the interrupt acknowledge

(INTA) signal is asserted in place of the read (RD) signal and

the address bus is held at the last valid logic state by internal

bus-hold devices (see Figure 6). In the second of two

successive INTA cycles, a byte of information is read from

the data bus, as supplied by the interrupt system logic (i.e.,

82C59A priority interrupt controller). This byte identiﬁes the

source (type) of the interrupt. It is multiplied by four and used

as a pointer into the interrupt vector lookup table, as

described earlier.

Bus Timing - Medium Complexity Systems

For medium complexity systems, the MN/MX pin is

connected to GND and the 82C88 bus controller is added to

the system, as well as an 82C82/82C83 latch for latching the

system address, and an 82C86/82C87 transceiver to allow

for bus loading greater than the 80C88 is capable of

handling (see Figure 8). Signals ALE, DEN, and DT/R are

generated by the 82C88 instead of the processor in this

conﬁguration, although their timing remains relatively the

same. The 80C88 status outputs (S2, S1 and S0) provide

type of cycle information and become 82C88 inputs. This

bus cycle information speciﬁes read (code, data or I/O), write

(data or I/O), interrupt acknowledge, or software halt. The

82C88 thus issues control signals specifying memory read

or write, I/O read or write, or interrupt acknowledge. The

82C88 provides two types of write strobes, normal and

advanced, to be applied as required. The normal write

strobes have data valid at the leading edge of write. The

advanced write strobes have the same timing as read

strobes, and hence, data is not valid at the leading edge of

write. The 82C86/82C87 transceiver receives the usual T

and OE inputs from the 82C88 DT/R and DEN outputs.

The pointer into the interrupt vector table, which is passed

during the second INTA cycle, can derive from an 82C59A

located on either the local bus or the system bus. If the

master 82C59A priority interrupt controller is positioned on

the local bus, the 82C86/82C87 transceiver must be

disabled when reading from the master 82C59A during the

interrupt acknowledge sequence and software “poll”.

The 80C88 Compared to the 80C86

The 80C88 CPU is a 8-bit processor designed around the

8086 internal structure. Most internal functions of the 80C88

are identical to the equivalent 80C86 functions. The 80C88

handles the external bus the same way the 80C86 does with

the distinction of handling only 8-bits at a time. Sixteen-bit

operands are fetched or written in two consecutive bus

cycles. Both processors will appear identical to the software

engineer, with the exception of execution time. The internal

same end result. Internally, there are three differences

between the 80C88 and the 80C86. All changes are related

to the 8-bit bus interface.

• The queue length is 4 bytes in the 80C88, whereas the

80C86 queue contains 6 bytes, or three words. The queue

was shortened to prevent overuse of the bus by the BIU

when prefetching instructions. This was required because

of the additional time necessary to fetch instructions 8-bits

at a time.

• To further optimize the queue, the prefetching algorithm

was changed. The 80C88 BIU will fetch a new instruction

to load into the queue each time there is a 1 byte space

available in the queue. The 80C86 waits until a 2 byte

space is available.

• The internal execution time of the instruction set is

affected by the 8-bit interface. All 16-bit fetches and writes

from/to memory take an additional four clock cycles. The

CPU is also limited by the speed of instruction fetches.

This latter problem only occurs when a series of simple

operations occur. When the more sophisticated instruc-

tions of the 80C88 are being used, the queue has time to

ﬁll the execution proceeds as fast as the execution unit will

allow.

80C88

MULTIBUS

™ is a patented Intel bus.

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