4-274

March 1997

82C82

CMOS Octal Latching Bus Driver

Features

• Full Eight-Bit Parallel Latching Buffer

• Bipolar 8282 Compatible

• Three-State Noninverting Outputs

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.

• Gated Inputs:

- Reduce Operating Power

- Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply

• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10

µA

• Operating Temperature Ranges

Description

The Intersil 82C82 is a high performance CMOS Octal

Latching Buffer manufactured using a self-aligned silicon

gate CMOS process (Scaled SAJI IV). The 82C82 provides

an eight-bit parallel latch/buffer in a 20 pin package. The

active high strobe (STB) input allows transparent transfer of

data and latches data on the negative transition of this sig-

nal. The active low output enable (OE) permits simple inter-

face to state-of-the-art microprocessor systems.

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG. NO.

CP82C82

20 Ld PDIP

E20.3

IP82C82

CS82C82

20 Ld PLCC

N20.35

IS82C82

CD82C82

20 Ld CERDIP

F20.3

ID82C82

MD82C82/B

8406701RA

SMD #

MR82C82/B

J20.A

84067012A

SMD #

Pinouts

82C82 (PDIP, CERDIP)

TOP VIEW

82C82 (PLCC, CLCC)

TOP VIEW

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

OE

GND

STB

19

3

2

20

1

15

16

17

18

14

9

10

11

12

13

4

5

6

7

8

TRUTH TABLE

STB

OE

DI

DO

X

H

X

Hi-Z

HL

L

L

HL

H

H

↓

LX

†

H

= Logic One

L

= Logic Zero

X

= Don’t Care

†

= Latched to Value of Last

Data

Hi-Z

= High Impedance

↓

= Neg. Transition

PIN NAMES

PIN

DESCRIPTION

Data Input Pins

Data Output Pins

STB

Active High Strobe

OE

Active Low Output

Enable

File Number

2975.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207