4-13

treats the RD following a “poll write” operation as an INTA.

After initialization, the 82C59A is set to lRR.

For reading the lMR, no OCW3 is needed. The output data bus

will contain the lMR whenever RD is active and A0 = 1 (OCW1).

Polling overrides status read when P = 1, RR = 1 in OCW3.

Edge and Level Triggered Modes

This mode is programmed using bit 3 in lCW1.

If LTlM = “0”, an interrupt request will be recognized by a low to

high transition on an IR input. The IR input can remain high

without generating another interrupt.

If LTIM = “1”, an interrupt request will be recognized by a “high”

level on an IR input, and there is no need for an edge detection.

The interrupt request must be removed before the EOI com-

mand is issued or the CPU interrupt is enabled to prevent a

second interrupt from occurring.

The priority cell diagram shows a conceptual circuit of the level

sensitive and edge sensitive input circuitry of the 82C59A. Be

sure to note that the request latch is a transparent D type latch.

In both the edge and level triggered modes the IR inputs

must remain high until after the falling edge of the first INTA.

If the IR input goes low before this time a DEFAULT lR7 will

occur when the CPU acknowledges the interrupt. This can

be a useful safeguard for detecting interrupts caused by spu-

rious noise glitches on the IR inputs. To implement this fea-

ture the lR7 routine is used for “clean up” simply executing a

return instruction, thus, ignoring the interrupt. If lR7 is

needed for other purposes a default lR7 can still be detected

by reading the ISR. A normal lR7 interrupt will set the corre-

sponding ISR bit, a default IR7 won’t. If a default IR7 routine

occurs during a normal lR7 routine, however, the ISR will

remain set. In this case it is necessary to keep track of

whether or not the IR7 routine was previously entered. If

another lR7 occurs it is a default.

In power sensitive applications, it is advisable to place the

82C59A in the edge-triggered mode with the IR lines nor-

mally high. This will minimize the current through the internal

pull-up resistors on the IR pins.

The Special Fully Nested Mode

This mode will be used in the case of a big system where

cascading is used, and the priority has to be conserved

within each slave. In this case the special fully nested mode

will be programmed to the master (using lCW4). This mode

is similar to the normal nested mode with the following

exceptions:

a. When an interrupt request from a certain slave is in ser-

vice, this slave is not locked out from the master’s priority

logic and further interrupt requests from higher priority

IRs within the slave will be recognized by the master and

will initiate interrupts to the processor. (In the normal

nested mode a slave is masked out when its request is in

service and no higher requests from the same slave can

be serviced.

b. When exiting the Interrupt Service routine the software

has to check whether the interrupt serviced was the only

one from that slave. This is done by sending a non-spe-

cific End of Interrupt (EOI) command to the slave and

then reading its In-Service register and checking for zero.

If it is empty, a non-specified EOI can be sent to the mas-

ter, too. If not, no EOI should be sent.

Buffered Mode

When the 82C59A is used in a large system where bus driv-

ing buffers are required on the data bus and the cascading

mode is used, there exists the problem of enabling buffers

The buffered mode will structure the 82C59A to send an

enable signal on SP/EN to enable the buffers. In this mode,

whenever the 82C59A’s data bus outputs are enabled, the

SP/EN output becomes active.

LATCH

ARM

(NOTE 1)

EARLIEST IR

CAN BE

REMOVED

LATCH

ARM

(NOTE 1)

8080/85

LATCH

ARM

(NOTE 1)

80C86/88/286

80C86/88/286

8080/85

IR

INT

INTA

NOTE:

1. Edge triggered mode only.

FIGURE 10. IR TRIGGERING TIMING REQUIREMENTS

82C59A