AD7276/AD7277/AD7278

Rev. C | Page 12 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CS

6

SCLK

4

SDATA

5

AD7276/

AD7277/

AD7278

TOP VIEW

(Not to Scale)

Figure 8. 6-Lead TSOT Pin Configuration

8

GND

7

SCLK

6

NC

5

NC = NO CONNECT

AD7276/

AD7277/

AD7278

TOP VIEW

(Not to Scale)

Figure 9. 8-Lead MSOP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

6-Lead TSOT

8-Lead MSOP

Mnemonic

Description

1

1

2

7

GND

Analog Ground. Ground reference point for all circuitry on the

AD7276/AD7277/AD7278. All analog input signals should be referred to this GND

voltage.

3

8

4

6

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the

part. This clock input is also used as the clock source for the conversion process of the

AD7276/AD7277/AD7278.

5

2

SDATA

Data Out. Logic output. The conversion result from the AD7276/AD7277/AD7278 is

provided on this output as a serial data stream. The bits are clocked out on the falling

edge of the SCLK input. The data stream from the AD7276 consists of two leading

zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first.

The data stream from the AD7277 consists of two leading zeros followed by 10 bits of

conversion data and four trailing zeros, provided MSB first. The data stream from the

AD7278 consists of two leading zeros followed by 8 bits of conversion data and six

trailing zeros, provided MSB first.

6

3

CS

Chip Select. Active low logic input. This input provides the dual function of initiating

conversion on the AD7276/AD7277/AD7278 and framing the serial data transfer.

4, 5

NC

No Connect.