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AMTP32M 数据表(PDF) 9 Page - Aplus Intergrated Circuits |
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AMTP32M 数据表(HTML) 9 Page - Aplus Intergrated Circuits |
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9 / 30 page ![]() Integrated Circuits Inc. aMTPxxM Series Ver 1.1 9/30 12/16/2014 CPU Parallel Mode Summary Support up to 32 voice section random play by 5 Addr pins and a TG pin. User assign voice section by Addr pins, and voice will play when TG pin rising edge. It also provides a BUSY output, the BUSY pin will output VIH when voice playing. Pin Defined Pin Name PB0 PB1 PB2 PB3 Description Addr[0] Addr[1] Addr[2] Addr[3] Pin Name PD0 PD1 PD2 Description BUSY Addr[4] Trigger P.S. 1. Addr[0] ~ Addr[4] are Section number in binary digit. 2. Addr[0] is the LSB (least signification bit), Addr[4] is the MSB (most signification bit). |
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