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CDP1823CD3 数据表(PDF) 3 Page - Intersil Corporation

部件名 CDP1823CD3
功能描述  High-Reliability CMOS 128-Word x 8-Bit Static RAM
PDF  6 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

CDP1823CD3 数据表(HTML) 3 Page - Intersil Corporation

  CDP1823CD3 Datasheet HTML 1Page - Intersil Corporation CDP1823CD3 Datasheet HTML 2Page - Intersil Corporation CDP1823CD3 Datasheet HTML 3Page - Intersil Corporation CDP1823CD3 Datasheet HTML 4Page - Intersil Corporation CDP1823CD3 Datasheet HTML 5Page - Intersil Corporation CDP1823CD3 Datasheet HTML 6Page - Intersil Corporation  
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6-33
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1823C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
60
17
Maximum Operating Temperature Range (TA) . . . .-55
oC to +125oC
Maximum Storage Temperature Range (TSTG) . . .-65
oC to +150oC
Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating
conditions should be selected so that operation is always within the following ranges:
PARAMETER
LIMITS
UNITS
MIN
MAX
Supply Voltage Range
4
6.5
V
Recommended Input Voltage Range
VSS
VDD
V
Static Electrical Specifications
VDD = 5V ±5%
PARAMETER
CONDITIONS
LIMITS
UNITS
VO
(V)
VIN
(V)
VDD
(V)
-55oC, +25oC
+125oC
MIN
MAX
MIN
MAX
Quiescent Device Current (Note 1)
IDD
-
0, 5
5
-
270
-
1000
µA
Output Low (Sink) Current (Note 1)
IOL
0.4
0, 5
5
2.7
-
1.5
-
mA
Output High (Source) Current (Note 1)
IOH
4.6
0, 5
5
-
-1.3
-
-0.7
mA
Output Voltage Low-Level
VOL
-
0, 5
5
-
0.1
-
0.1
V
Output Voltage High-Level
VOH
-
0, 5
5
VDD - 0.1
-
VDD - 0.1
-
V
Input Low Voltage
VIL
0.5, 4.5
-
5
-
0.3 VDD
-
0.3 VDD
V
Input High Voltage
VIH
0.5, 4.5
-
5
0.7 VDD
-
0.7 VDD
-V
Input Leakage Current (Note 1)
IIN
-
0, 5
5
-
±2.6
-
±10
µA
Operating Current (Note 1)
IDD1
-
0, 5
5
-
5
-
10
mA
Three-State Output Leakage Current
IOUT
0, 5
0, 5
5
-
±2.6
-
±10
µA
Input Capacitance
CIN
-
-
-
-
7.5
-
7.5
pF
Output Capacitance
COUT
--
--
15
-
15
pF
NOTE:
1. Limits designate 100% testing, all other limits are designer’s parameters under given test conditions and do not represent 100% testing.
Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF
PARAMETER
SYMBOL
VDD
(V)
LIMITS
UNITS
+25oC, -55oC
+125oC
MIN
MAX
MIN
MAX
Read Cycle
tRC
5
360
-
505
-
ns
Access Time from Address Change (Note 1)
tAA
5
-
360
-
505
ns
Access Time from Chip Select
tAC
5
-
360
-
505
ns
CDP1823C/3



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