6-35

Data Hold Time from MWR (Note 1)

5

50

-

70

-

ns

Chip Select Setup

5

210

-

300

-

ns

NOTES:

1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.

2. Minimum timing to allow the indicated function to occur.

PARAMETER

SYMBOL

(V)

LIMITS

UNITS

(NOTE 2)

MIN

MAX

(NOTE 2)

MIN

MAX

ADDRESS

VALID DATA

CS1, CS4

CS2, CS3, CS5

MWR

BUS 0-7

NOTE:

1. MRD must be high during write operation.

FIGURE 2. WRITE CYCLE TIMING WAVEFORMS

Data Retention Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

LIMITS

UNITS

(V)

(V)

MIN

MAX

MIN

MAX

Minimum Data Retention Voltage

(Note 1)

-

-

-

2

-

2.5

V

Data Retention Quiescent Current

2

-

-

100

-

400

µA

Chip Deselect to Data Retention Time

-

5

450

-

650

-

ns

Recovery to Normal Operation Time

-

5

450

-

650

-

ns

NOTE:

1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.

CDP1823C/3