5-44

Block Diagram

Mode Input High (Mode = 1)

NOTE: 1. User Interconnect

FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)

SELECT

LOGIC

23

4

35

INT

13

STATUS

REGISTER

22

14

15

19

CONTROL

REG

TRANSMITTER

HOLDING

REGISTER

TRANSMITTER BUS

(26 - 33)

(SEE NOTE 1)

TRANSMITTER

SHIFT

REGISTER

PARITY

GEN

THREE-STATE

DRIVERS

RECEIVER BUS

(5-12)

(SEE NOTE 1)

(SEE NOTE 1)

MUX

TRANSMITTER

TIMING &

CONTROL

40

24

39

TRANSMITTER SECTION

RECEIVER

TIMING &

CONTROL

38

37

17

RECEIVER SECTION

RECEIVER

HOLDING

REGISTER

SHIFT

REGISTER

CDP1802

INTERFACE

34

18

16

20

SDI

25

SDO

21 = CLEAR

36 = NC

CDP1854A, CDP1854AC