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HCS193K 数据表(PDF) 1 Page - Intersil Corporation |
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HCS193K 数据表(HTML) 1 Page - Intersil Corporation |
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1 / 9 page  270 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS193DMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCS193KMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack HCS193D/Sample +25oC Sample 16 Lead SBDIP HCS193K/Sample +25oC Sample 16 Lead Ceramic Flatpack HCS193HMSR +25oC Die Die HCS193MS Radiation Hardened Synchronous 4-Bit Up/Down Counter Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 Q1 Q0 CPD CPU Q2 GND Q3 MR TCD TCU PL P2 P0 P1 VCC P3 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 Q1 Q0 CPD CPU Q2 GND Q3 P1 MR TCD TCU PL P2 P0 VCC P3 Features • 3 Micron Radiation Hardened CMOS SOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit- Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.30% VCC Max - VIH = 0.70% VCC Min • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCS193MS is a Radiation Hardened 4-bit binary UP/ DOWN synchronous counter. Presetting the counter to the number on the preset data inputs (P0 - P3) is accomplished by a low on the asynchronous parallel load input (PL). The counter is incremented on the low to high transition of the clock-up input (high on the clock-down), decremented on the low to high transition of the clock-down input (high on the clock-up). A high level on the MR input overrides any other input to clear the counter to zero. The Terminal Count Up goes low half a clock period before the zero count is reached and returns high at the maximum count. The HCS193MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. September 1995 Spec Number 518759 File Number 3065.1 |
类似零件编号 - HCS193K |
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类似说明 - HCS193K |
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