 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
HCS573HMSR 数据表(PDF) 1 Page - Intersil Corporation |
|
|
|||||||||||||||||||||||||||||
HCS573HMSR 数据表(HTML) 1 Page - Intersil Corporation |
|
|
1 / 10 page  324 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS573DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP HCS573KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack HCS573D/Sample +25oC Sample 20 Lead SBDIP HCS573K/Sample +25oC Sample 20 Lead Ceramic Flatpack HCS573HMSR +25oC Die Die HCS573MS Radiation Hardened Octal Transparent Latch, Three-State Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20, LEAD FINISH C TOP VIEW 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 OE D0 D1 D2 D3 D4 D6 D5 D7 GND VCC Q1 Q2 Q3 Q0 Q4 Q5 Q6 Q7 LE 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 OE D0 D1 D2 D3 D4 D5 D6 9 10 12 11 D7 GND VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit- Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCS573MS is a Radiation Hardened octal transpar- ent three-state latch with an active low output enable. The HCS573MS utilizes advanced CMOS/SOS technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the tri-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. The HCS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS573MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). September 1995 Spec Number 518771 File Number 4056 |
类似零件编号 - HCS573HMSR |
|
类似说明 - HCS573HMSR |
|
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
