HIP7010P datasheet(13/20 Pages) INTERSIL

13 / 20 page

lost the Host no longer needs to continue transmit-

ting bytes. As in the case of Type 2 IFRs, the Host

cannot know arbitration has been lost until after the

next byte to transmit has been loaded. Again, there

is no danger of sending extra bytes because the

HIP7010 automatically suspends transmissions

once arbitration is lost.

B6, MACK The Multi-byte Acknowledge (MACK) bit, in con-

junction with the ACK bit, signals the HIP7010 that,

following the EOD, a Type 3 IFR with CRC

response is to be sent. Once set, the MACK bit

cannot be cleared by the Host. MACK is cleared

upon detection of an Idle following the transmis-

sion of the IFR. Setting MACK without also setting

ACK will result in no IFR being transmitted.

The MACK bit can be set anytime prior to 135

µs

after the ﬁnal byte (the CRC) of a message. The

ﬁrst IFR byte must be loaded into the Host’s serial

output register, and the RDY line set after the

HIP7010 transfers the next-to-last byte to the Host,

and before the HIP7010 transfers the last byte

(CRC) of the J1850 message to the Host. When

the CRC byte is sent to the Host from the

HIP7010, the ﬁrst IFR byte will be simultaneously

loaded into the HIP7010. To send a Type 3 IFR the

Host uses the short format of the RDY for all bytes

except the last, when the long format is used.

Setting the MACK bit in the Control Register is not

immediately reﬂected in the MACK bit of the Status

data transfer.

B5, NXT

If the Wait for Next Idle (NXT) bit is asserted high

during a Status/Control Register transfer, the

HIP7010 State Machine is re-initialized to a “wait

for Idle” state. The VPWOUT pin is driven low and

the IDLE pin is reset high. Activity on the VPWIN

pin is ignored until a valid Idle is detected. When

NXT is asserted the IDLE pin will go high for a min-

imum of 6

µs. If the bus is Idle at the end of the 6µs

period, IDLE will be driven low and the HIP7010

will be ready to transmit or receive a J1850 mes-

sage. If the bus is not Idle, current activity on the

VPWIN pin is ignored until a new Idle is detected.

The NXT bit enables the Host to ignore the bal-

ance of the current message. Unsolicited transfers

from the HIP7010 are guaranteed not to occur until

the next Idle occurs. Transfers resume following

the ﬁrst byte of the next message.

B4, PD

The Power-Down (PD) bit is used to halt internal

clocks to the HIP7010 to minimize power. A low

level on the VPWIN, a low to high edge on the

STAT pin, or a high level on the RDY pin will clear

the PD bit and normal HIP7010 functions will

resume.

PD can only be set if the IDLE pin is low or during

the ﬁrst Status/Control Register transfer following

a reset. The CLK input is internally gated off at

the end of the Status/Control Register transfer.

There are two situations which can cause the PD

bit to be cleared prematurely: 1. The RDY input is

high during the Status/Control Register transfer

(since this is under control of the Host it should be

avoided); 2. A noise pulse of less than 7

µs dura-

tion occurs on the VPWIN line.

If either of these situations occur, the PD will be

cleared, the HIP7010 will resume operating and

look for a valid edge on VPWIN, RDY, or STAT. If

no valid edge has occurred the HIP7010 will recy-

cle to the top of the State Machine, pulsing IDLE

high for a minimum of 2

µs. It is the responsibility

of the Host to monitor the IDLE pin after setting

PD to ensure that the POWER-DOWN mode has

been successfully entered.

See Effects of Resets and Power-Down for a

detailed discussion of the Power-Down mode.

B3, 4X

Setting the High Speed Mode (4X) bit causes the

HIP7010’s SENDEC to decode symbols received

on the J1850 bus at 0.25X the normal durations.

The 4X mode is designed to allowed receipt of mes-

sages at 4X the normal J1850 rate. It is intended for

manufacturing and diagnostic use, not normal

“down the road” vehicle communications. Transmis-

sion is inhibited while the 4X bit is set.

The 4X bit can only be written to when the IDLE

pin is low or during the ﬁrst Status/Control transfer

following a reset. Setting 4X is inhibited during the

ﬁrst Status/Control after a Break. The SENDEC

begins operating at the 4X rate upon receipt of the

next edge. The system must provide sufﬁcient time

for all nodes to detect the Idle, interpret the “shift to

high speed” message, and change their mode bits

before issuing a high speed SOF.

4X is cleared by receipt of a Break symbol on the

J1850 bus and it can also be cleared by perform-

ing a Status/Control Register transfer with the 4X

bit low. When cleared via a Status/Control Regis-

ter transfer, IDLE must be low. The SENDEC

reverts to operating at the normal rate upon

receipt of the next edge.

4X mode cannot be utilized for transmitting mes-

sages. VPWOUT is disabled in hardware, but the

State Machine will attempt to transmit if RDY is

strobed. It is the Host’s responsibility to refrain

from transmitting in 4X mode.

B2, DS2, B1, DSI, B0, DSI

The three Divide Select bits (DS2-DS0) are used

to match the internal clock divider with the input

frequency on the CLK input to produce the

required 2MHz internal time base. Table 3 shows

the clock divide values and nominal input fre-

quency for the eight combinations of DS2-DS0.

HIP7010

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