2

Block Diagram

Applications

The circuit of Figure 1 illustrates the essential elements of

the J1850 Bus Transceiver in a normal application. For nor-

mal J1850 applications, a Bus Transceiver is used at each

system node. The Electrical Specifications Table also refers

to the peripheral components shown in Figure 1 and the

Block Diagram for the HIP7020 Bus Transceiver.

possible to the IC to minimize noise coupling to the R/F

to the GND pin of the IC with no other current flowing in

the connecting line to prevent system ground currents

from affecting the rise/fall time control of the Wave

tolerance. If an R/F bypass capacitor is used to filter

noise, the value should be 100pF or less. For effective

noise filtering, the R/F bypass capacitor should be con-

nected direct from the R/F pin to the GND pin and should

not carry current from other sources.

Figure 2 illustrates some of the typical J1850 System

Configurations that utilize the HIP7020 Bus Transceiver.

Refer to the HIP7010 and HIP7030A2 Data Sheets for

further information on J1850 System Configuration detail.

TX

WAVE

SHAPER

WAVE

VOLT. REF

SHAPED

VOLTAGE TO

CONVERTER

FILTER

BUS RCVR AND

VOLT. COMP.

RX

TX

RX

BUS OUT

BUS IN

BATT

CURRENT

LOOP-BACK

OVER-

V+

HIP7020

Q1

LB EN

DIAGNOSTIC

BUF

BUF

LEVEL

SHIFTER

TEMP SW

LOOP-BACK MODE

R/F

TIME

GND

R/F TIME

0.01

µF

C1

M1

CONTROLLER

BUS OUT

BUS IN

BATT

GND

J1850 BUS

RX

TX

J1850 BUS

TRANSCEIVER

R/F

LB EN

MOV

10

15K

56.2K

HIP7030A2

(NOTE)

NOTE: MOV, M1 represents central protection, normally on the

alternator and with a typical value in the range of 27V to 40V.

FIGURE 1. TYPICAL APPLICATION CIRCUIT DIAGRAM

µC

HOST

HIP7010

BYTE LEVEL

HIP7020

BUS

TRANSCEIVER

INTERFACE

CIRCUIT

µC

HOST

HIP7030A2

HIP7020

BUS

TRANSCEIVER

µC

HIP7020

BUS

TRANSCEIVER

HIP7030A2

µC

FIGURE 2. TYPICAL J1850 SYSTEM CONFIGURATIONS

HIP7020