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ADM4853 数据表(PDF) 8 Page - Analog Devices |
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ADM4853 数据表(HTML) 8 Page - Analog Devices |
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8 / 16 page ![]() ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 8 of 16 VCC 1 A 8 GND 4 Y 5 ADM4854/ ADM4855/ ADM4856/ ADM4857 TOP VIEW (Not to Scale) RO 2 B 7 DI Z 6 3 Figure 5. ADM4854/ADM4855/ADM4856/ADM4857 Pin Configuration, SOIC Table 9. ADM4854/ADM4855/ADM4856/ADM4857 Pin Descriptions Pin No. Mnemonic Description 1 VCC 5 V Power Supply. 2 RO Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low. 3 DI Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low. 4 GND Ground. 5 Y Noninverting Driver Output. 6 Z Inverting Driver Output. 7 B Inverting Receiver Input. 8 A Noninverting Receiver Input. |
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