R5F10366ASP datasheet(77/110 Pages) RENESAS

77 / 110 page

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: TA =

−40 to +105°C)

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 77 of 106

3.5 Peripheral Functions Characteristics

AC Timing Test Point

VIH/VOH

VIL/VOL

Test points

VIH/VOH

VIL/VOL

3.5.1 Serial array unit

(1) During communication at same potential (UART mode)

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

Transfer rate

Note 1

fMCK/12

bps

Theoretical value of the maximum transfer rate

fCLK = fMCK

Note2

2.0

Mbps

Notes 1.

Transfer rate in the SNOOZE mode is 4800 bps only.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode: 24 MHz (2.7 V

≤ VDD ≤ 5.5 V)

16 MHz (2.4 V

≤ VDD ≤ 5.5 V)

Caution

Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by

using port input mode register g (PIMg) and port output mode register g (POMg).

UART mode connection diagram (during communication at same potential)

RL78

microcontroller

TxDq

RxDq

User's device

UART mode bit width (during communication at same potential) (reference)

TxDq

RxDq

Baud rate error tolerance

High-/Low-bit width

1/Transfer rate

Remarks 1.

q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial

mode register mn (SMRmn).

m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))

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