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R5F3650ECNFB 数据表(PDF) 21 Page - Renesas Technology Corp |
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R5F3650ECNFB 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 112 page  R01DS0015EJ0110 Rev.1.10 Page 21 of 109 Jul 31, 2012 M16C/65C Group 1. Overview Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration allows VCC2 to interface at a different voltage than VCC1. Table 1.15 Pin Functions for the 100-Pin Package (1/3) Signal Name Pin Name I/O Power Supply Description Power supply input VCC1, VCC2, VSS I- Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2) and 0 V to the VSS pin. Analog power supply input AVCC, AVSS I VCC1 This is the power supply for the A/D and D/A converters. Connect the AVCC pin to VCC1, and connect the AVSS pin to VSS. Reset input RESET I VCC1 Driving this pin low resets the MCU. CNVSS CNVSS I VCC1 Input pin to switch processor modes. After a reset, to start operating in single-chip mode, connect the CNVSS pin to VSS via a resistor. To start operating in microprocessor mode, connect the pin to VCC1. External data bus width select input BYTE I VCC1 Input pin to select the data bus of the external area. The data bus is 16 bits when it is low, and 8 bits when it is high. This pin must be fixed either high or low. Connect the BYTE pin to VSS in single-chip mode. Bus control pins D0 to D7 I/O VCC2 Inputs or outputs data (D0 to D7) while accessing an external area with a separate bus. D8 to D15 I/O VCC2 Inputs or outputs data (D8 to D15) while accessing an external area with a 16-bit separate bus. A0 to A19 O VCC2 Outputs address bits A0 to A19. A0/D0 to A7/D7 I/O VCC2 Inputs or outputs data (D0 to D7) and outputs address bits (A0 to A7) by timesharing, while accessing an external area with an 8-bit multiplexed bus. A1/D0 to A8/D7 I/O VCC2 Inputs or outputs data (D0 to D7) and outputs address bits (A1 to A8) by timesharing, while accessing an external area with a 16-bit multiplexed bus. CS0 to CS3 O VCC2 Outputs chip-select signals CS0 to CS3 to specify an external area. WRL/WR WRH/BHE RD O VCC2 Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and WRH can be switched with BHE and WR. • WRL, WRH, and RD selected If the external data bus is 16 bits, data is written to an even address in an external area when WRL is driven low. Data is written to an odd address when WRH is driven low. Data is read when RD is driven low. • WR, BHE, and RD selected Data is written to an external area when WR is driven low. Data in an external area is read when RD is driven low. An odd address is accessed when BHE is driven low. Select WR, BHE, and RD when using an 8-bit external data bus. ALE O VCC2 Outputs an ALE signal to latch the address. HOLD I VCC2 HOLD input is unavailable. Connect the HOLD pin to VCC2 via a resistor (pull-up). HLDA O VCC2 In a hold state, HLDA outputs a low-level signal. RDY I VCC2 The MCU bus is placed in a wait state while the RDY pin is driven low. |
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