ACE25C320G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

29

Figure28. Write Enable for Volatile Status Register

Power – On Timing

Table3. Power-Up Timing And Write Inhibit Threshold

Symbol

Parameter

Min

Max

Unit

tVSL

VCC(min) To CS# Low

10

us

tPUW

Time Delay From VCC(min) To Write Instruction

1

10

ms

VWI

Write Inhibit Voltage VCC(min)

1

2.5

V

Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1(each byte contains

FFH).The Status Register contains 00H (all Status Register bits are 0).

Data Retention And Endurance

Parameter

Test Condition

Min

Units

Minimum Pattern Data Retention Time

150℃

10

Years

125℃

20

Years

Erase / Program Endurance

-40 to 85 ℃

100K

Cycles