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UPD16337 数据表(PDF) 8 Page - NEC

部件名 UPD16337
功能描述  64-BIT AC-PDP DRIVER
PDF  16 Pages
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制造商  NEC [NEC]
网页  http://www.nec.com/
标志 NEC - NEC

UPD16337 数据表(HTML) 8 Page - NEC

Back Button UPD16337 Datasheet HTML 4Page - NEC UPD16337 Datasheet HTML 5Page - NEC UPD16337 Datasheet HTML 6Page - NEC UPD16337 Datasheet HTML 7Page - NEC UPD16337 Datasheet HTML 8Page - NEC UPD16337 Datasheet HTML 9Page - NEC UPD16337 Datasheet HTML 10Page - NEC UPD16337 Datasheet HTML 11Page - NEC UPD16337 Datasheet HTML 12Page - NEC Next Button
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µPD16337
8
SWITCHING CHARACTERISTICS (TA = 25
°C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V, logic CL
= 15 pF, driver CL = 50 pF, tr = tf = 6.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transmission Delay Time
tPHL1
CLK
↓ → A/B
40
ns
tPLH1
40
ns
tPHL2
CLK
↑ (LE = H) → O1 to O64
180
ns
tPLH2
180
ns
tPHL3
BLK
→ O1 to O64
165
ns
tPLH3
165
ns
tPHL4
PC
→ O1 to O64
160
ns
tPLH4
160
ns
Rise Time
tTLH
O1 to O64
200
ns
Fall Time
tTHL
O1 to O64
200
ns
Maximum Clock Frequency
fmax.
When data is read, duty 50%
25
MHz
TA = –40 to +85
°C
VDD1 = 4.5 to 5.5 V
When a cascade connection is
20
MHz
made with a duty of 50%
TA = –40 to +85
°C
VDD1 = 4.5 to 5.5 V
Input Capacitance
CI
15
pF
TIMMING REQUIREMENT (TA = –40 to +85
°C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Clock Pulse Width
PWCLK
20
ns
Latch Enable Pulse Width
PWLE
30
ns
Blank Pulse Width
PWBLK
500
ns
PC Pulse Width
PWPC
500
ns
Data Setup Time
tsetup
10
ns
Data Hold Time
thold
10
ns
Latch Enable Time 1
tLE1
20
ns
Latch Enable Time 2
tLE2
10
ns
Latch Enable Time 3
tLE3
20
ns
Latch Enable Time 4
tLE4
10
ns



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