R5F2136CSDFP datasheet(39/61 Pages) RENESAS

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R8C/36T-A Group

4. Electrical Characteristics

R01DS0055EJ0100 Rev.1.00

Page 39 of 58

Dec 09, 2011

Figure 4.2

Time Delay from Suspend Request until Suspend

Notes:

1. The voltage detection level must be selected with bits VDSEL0 and VDSEL1 in the OFS register.

2. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

Table 4.7

Voltage Detection 0 Circuit Characteristics

(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr =

20°C to 85°C (N version)/

40°C to 85°C (D version))

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

Vdet0

Voltage detection level Vdet0_0 (1)

When Vcc falls

1.80

1.90

2.05

Voltage detection level Vdet0_1 (1)

When Vcc falls

2.15

2.35

2.55

Voltage detection level Vdet0_2 (1)

When Vcc falls

2.70

2.85

3.05

Voltage detection level Vdet0_3 (1)

When Vcc falls

3.55

3.80

4.05

―

Voltage detection 0 circuit response time (2)

At the falling of Vcc from 5 V

to (Vdet0

 0.1) V

―

150

μs

―

Voltage detection circuit self power

consumption

VCA25 = 1, Vcc = 5.0 V

―

1.5

―μA

td(E-A)

Waiting time until voltage detection circuit

operation starts (3)

――

100

μs

FST6 bit

Suspend request

(FMR21 bit)

Fixed time

Clock-dependent

time

Access restart

FST6: Bit in FST register

FMR21: Bit in FMR2 register

td(SR-SUS)

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