AN4076

Current sensing circuit design guidelines

Doc ID 022923 Rev 1

7/14

Although oscillations may be reduced by minimizing the parasitic inductance of the traces

(proportional to their length and inversely proportional to their width), some filtering is

always necessary to clean up the feedback signal and possibly make it go to its steady-state

faster, enlarging in this way the range of time during which the current feedback signals may

be read by the downstream microcontroller unit.

On the other hand, the filtering can't be too strong because, as already mentioned, the

current flows in the shunt resistor only during the on-time of the low-side switch. Considering

that the duty cycle applied to this transistor can be very low and that the FOC algorithm

requires the current to be read each PWM cycle, having a strong filtering would in fact result

in a sensible limitation of the minimum duty cycle applicable (i.e. of the bus voltage

exploitation) for keeping the current reading possible.

A tailoring of the filtering stage would be then required for each new design (as it depends

on the speed of the switch turn-on, the diode recovery charge, the parasitic inductances,

etc.). As a general guideline, an RC filter with a time constant between 100 ns and 200 ns

usually accomplishes this task pretty well. If necessary, a further RC filter with similar time

constant may be added in the amplifying section by putting a capacitor (C2 in Figure 3) in

parallel to the feedback resistor.

1.3

Amplification section

After each of the signals on the shunt resistors have been filtered, amplification is required

for each of them in order to adapt the signals to the range of voltage that can be read by the

analog-to-digital converter (ADC) peripheral embedded in the microcontroller unit (MCU).

The non-inverting configuration shown in Figure 3 is usually used in STEVAL boards.

As can be seen, as the signal on the shunt resistor can be both positive and negative, while

the MCU can only read positive voltage, an offset is added (R2, R3) so that the output of the

op amp equals about half of the MCU supply voltage when no current flows in the shunt

resistor. This offset stage, on the other hand, introduces attenuation (1/G1) of the useful

signal which, together with the gain of the non-inverting configuration (G2, fixed by R4 and

R5), contributes to the overall gain (G).

As mentioned, the goal here is to establish the overall amplification network gain (G) so that

particular, gain G and polarization voltage on the output should be chosen so that the range

covers between 85% and 90% of the

not perfect current regulation.

It's clear that in order to maximize the op amp output swing, and therefore the current

reading accuracy, it is better to use output rail-to-rail amplifiers able to reach very low

voltages (tens of mV) and voltages very close to supply voltage (in case this is the same as

ADC supply voltage) before saturating.

It must be noted that, once G is fixed, it is better to compose it by lowering the initial

attenuation 1/G1 as much as possible and, therefore, also gain G2. This is important not

only to maximize the signal by noise ratio but also to reduce the effect of the op amp intrinsic

offset on the output (proportional to G2).

The attached spreadsheet ('Current sensing amplification stage design tool.xlsx ') is

intended to be used as a tool for helping designers find the proper values of the resistor

GR

shunt

I

I

Smax

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